The present invention relates to the operation and manufacture of integrated circuits. More specifically, in one embodiment the invention provides improved dynamic random access memories (DRAMs), methods of operating dynamic random access memories and methods of making dynamic random access memories.
In the attempt to increase the number of bits on present DRAMs, methods are sought for shrinking device dimensions while still maintaining high enough capacitance in the storage capacitors so that data can be reliably stored, refreshed and read. For example, new dynamic random access memories are disclosed in application Ser. No. 08/353,788, filed Dec. 12, 1994, and U.S. Pat. No. 5,396,452, each of which is hereby incorporated by reference, wherein a memory cell contains separate read and write transistors.
In another example, substantial space could be saved merely by providing smaller capacitors in present DRAMs. However, smaller capacitors are generally refreshed more often than larger capacitors, as it can be assumed that the leakage current is the same. The capacitance of a bit line is proportional to the number of bits on the bit line. The refresh power consumption is proportional to the frequency of refresh cycles multiplied by the number of bits per bit line, where the refresh frequency is inversely proportional to the cell capacitor size. Therefore, the space advantages of a DRAM with smaller capacitors are mitigated by the higher power consumption of the required additional refresh cycles.
From the above examples it is seen that an improved dynamic random access memory is needed, along with improved methods of operating such memories and improved methods of making such memories.
The present invention is directed, in one embodiment, to a memory structure having short bit line segments. Each bit line segment is coupled to a separate block of memory cells and a corresponding amplifier. The bit line segments are separated by pass transistors. The amplifiers are activated in all three modes of operation: read mode, write mode and refresh mode, while the pass transistors are enabled only in connection with data input and output. Very small cell capacitors can be used in this configuration, making it possible to use conventional gate capacitors, but power consumption is not appreciably increased. Furthermore, the speed of the memory for read and write operations is faster than present DRAMs with long continuous bit lines coupled to a single amplifier.
In another aspect of the invention a memory is provided wherein the contents of the memory can be read without any interference from ongoing writing, reading and refreshing. The memory is structured in two tiers, meaning that in addition to a first tier, a DRAM with addressing, reading, writing and refreshing, a second tier with separate addressing from the first tier is used to read the contents of the cells in the first tier.
Improved methods of forming a dynamic random access memory are further provided according to the present invention. For example, in one aspect of the invention, a method is provided for forming a memory cell for use with programmable logic devices that must be controlled with relatively large capacitors. In programmable logic devices, pass transistors transfer signals between locations in the device. The controlling capacitor must be significantly larger than the gate capacitance of the pass transistor, so that the voltage on the controlling capacitor is relatively constant during the signal transition. A multi-layer approach to forming the memory allows the controlling capacitor to be located underneath the pass transistors and the memory cell transistors.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.